In a computer system including a CPU, a memory sub-system and a network controller, a PCI bus may be provided to support communications of the network controller with the CPU and the memory. When a process running on such a system sends a message over the network, it is necessary for the CPU to convey to the network the existence of the message and its content. To perform this task in an efficient way, instead of placing the required information into registers of the network controller, the CPU stores it in the memory sub-system. The network controller accesses this information using PCI bus master operations.
In order to minimize the number of access operations, the information should reside in structures of the memory sub-system having fixed addresses. Because the message may be quite large, its data is not stored in such structures. Instead the structures contain such information as the start address and length of the actual data regions. Each element in such a structure is referred to as a “descriptor”.
There are several different ways of organizing descriptors. For example, descriptors may be arranged in a linear list having a fixed beginning and a fixed or variable length. A variation of the linear list is a descriptor ring, in which the first descriptor logically follows the last. The ring includes a suitable semaphore system that allows both the network controller and the CPU to determine at any particular time whether the contents of any particular descriptor are valid and whether it is allowed to alter to contents of that descriptor.
Frames sent on a network are often comprised of data from several sources. They typically contain some network header information followed by headers from one or more higher level protocols inserted before the data. It is most efficient for the network controller to gather these headers and data from buffers in separate regions of the memory sub-system, rather than require the CPU to copy everything to a single, contiguous buffer in the memory sub-system. Thus, a single frame requires storing many buffer addresses and lengths.
To convey this information to the network controller, one descriptor may be provided to define each buffer in the memory sub-system. The network controller has a mechanism to determine which descriptor is the first descriptor of a frame, and which is the last.
When the network controller is informed of the existence of a frame to transmit, the network controller must read the first descriptor associated with the frame, examine it for correctness and read the data associated with that descriptor. This descriptor read is performed by the network controller acting as a PCI bus master.
When a device requests the PCI bus, there is some delay before the request is granted and the bus becomes available. After the memory read command is issued, there is a further delay before the memory sub-system returns the first double word of data. Such delays reduce the speed of transmission and increase the PCI bus bandwidth required for the network controller.
Accordingly, it would be desirable to create a descriptor read mechanism that allows PCI bus delays to be reduced.